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mitsubishi lsis m5m29fb/t800fp,vp,rv-80,-10,-12 may 1997 , rev.6.1 8,388,608-bit (1048,576-word by 8-bit / 524,288-word by16-bit) cmos 3.3v-only, block erase flash memory 1 mitsubishi lsis description the mitsubishi m5m29fb/t800fp, vp, rv are 3.3v-only high speed 8,388,608-bit cmos boot block flash memories suitable for mobile and personal computing, and communication products. the m5m29fb/t800fp, vp, rv are fabricated by cmos technology for the peripheral circuits and dinor(divided bit line nor) architecture for the memory cells, and are available in 44pin sop or 48pin tsop(i). features pin configuration (top view) organization 524,288 word x 16bit 1,048,576 word x 8 bit supply voltage ................................ v cc = 3.3v?.3v access time 80/100/120ns (max) power dissipation read 108 mw (max.) program/erase 144 mw (max.) standby 0.72 mw (max.) deep power down mode 3.3? (typ.) auto program program time 7.5ms (typ.) program unit 128word auto erase erase time 50 ms (typ.) erase unit boot block 8kword / 16kbyte x 1 parameter block 4kword / 8kbyte x 2 main block 16kword / 32kbyte x 1 32kword / 64kbyte x 15 program/erase cycles 100kcycles boot block m5m29fb800 bottom boot m5m29ft800 top boot other functions software command control selective block lock erase suspend/resume program suspend/resume status register read sleep package 48-lead, 12mmx 20mm tsop (type-i) 44-lead sop 8,388,608-bit (1048,576-word by 8-bit / 524,288-word by16-bit) cmos 3.3v-only, block erase flash memory m5m29fb/t800fp,vp,rv-80,-10,-12 1 nc : no connection rv(reverse bend): 48p3r-c outline 48pin tsop type-i (12 x 20mm) vp(normal bend): 48p3r-b this product is compatible with hn29wb/t800 by hitachi ltd. 1 2 3 4 5 6 7 8 9 10 44 43 42 41 40 38 37 35 11 12 34 33 39 36 13 32 14 31 15 30 16 29 m5m29fb/t800fp 17 28 18 27 19 26 20 25 outline 600mil 44-pin sop (fp: 44p2a-a) 21 24 22 23 ................................. .............................. ....................... ....................... ....................... ................................. ................................. ........................ ............................. ................................. ........................... ................................. ....................... ....................... ....................... a 15 a 12 a 10 dq 5 dq 12 a 8 a 13 a 14 dq 4 /we a 9 v cc gnd a 16 /rp dq 13 a 11 dq 6 dq 7 dq 14 dq15/a-1 /byte /ce a 7 a 5 a 4 dq 0 dq 1 dq 2 dq 3 a 3 a 2 a 1 a 17 a 18 dq 11 dq 10 dq 9 dq 8 /oe gnd a 0 a 6 address inputs address inputs chip enable input byte enable input reset/ power down input write enable input data inputs/ outputs data inputs/ outputs output enable input 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 a 18 a 17 a 16 ry/by nc a 11 a 10 m5m29fb/t800vp a 15 /ce 17 18 19 20 28 27 26 25 dq 0 a 0 21 22 23 24 48 47 46 45 a 13 a 12 a 14 gnd /oe a 9 a 8 nc nc /rp a 7 a 6 a 5 a 4 a 1 a 2 a 3 /we /byte dq 8 dq 1 dq 9 dq 2 v cc gnd dq 10 dq 3 dq 11 dq 4 dq 12 dq 5 dq 13 dq 6 dq 14 dq 7 dq 15 /a-1 /wp application code storage pc bios digital cellular phone/telecommunication 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 ry/by m5m29fb/t800rv a 15 17 18 19 20 28 27 26 25 21 22 23 24 48 47 46 45 a 14 gnd a 18 a 17 a 7 a 6 a 5 a 4 a 1 a 2 a 3 nc /rp a 11 a 10 a 9 a 8 nc nc a 13 a 12 /we /ce dq 0 a 0 /oe dq 8 dq 1 dq 9 dq 2 /wp v cc gnd dq 10 dq 3 dq 11 dq 4 dq 12 dq 5 dq 13 dq 6 dq 14 dq 7 dq 15 /a-1 a 16 /byte nc ........................... ........................... .......................................
mitsubishi lsis m5m29fb/t800fp,vp,rv-80,-10,-12 may 1997 , rev.6.1 8,388,608-bit (1048,576-word by 8-bit / 524,288-word by16-bit) cmos 3.3v-only, block erase flash memory 2 function block diagram deep power-down when /rp is at vil, the device is in the deep powerdown mode and its power consumption is substantially low. during read modes, the memory is deselected and the data input/output are in a high-impedance(high-z) state. after return from powerdown, the cui is reset to read array , and the status register is cleared to value 80h. during block erase or program modes, /rp low will abort either operation. memory array data of the block being altered become invalid. x-decoder y-decoder y-gate / sense amp. input/output buffers /ce /oe /we v cc (3.3v) gnd (0v) data inputs/outputs the m5m29fb/t800fp,vp,rv includes on-chip program/erase control circuitry. the write state machine (wsm) controls block erase and page program operations. operational modes are selected by the commands written to the command user interface (cui). the status register indicates the status of the wsm and when the wsm successfully completes the desired program or block erase operation. a deep powerdown mode is enabled when the /rp pin is at gnd, minimizing power consumption. read the m5m29fb/t800fp,vp,rv has three read modes, which accesses to the memory array, the device identifier and the status register. the appropriate read command are required to be written to the cui. upon initial device powerup or after exit from deep powerdown, the m5m29fb/t800 automatically resets to read array mode. in the read array mode, low level input to /ce and /oe, high level input to /we and /rp, and address signals to the address inputs (a0-a18) output the data of the addressed location to the data input/output(d0-15). write writes to the cui enables reading of memory array data, device identifiers and reading and clearing of the status register. they also enable block erase and program. the cui is written by bringing /we to low level, while /ce is at low level and /oe is at high level. address and data are latched on the earlier rising edge of /we and /ce. standard micro-processor write timings are used. d 15 /a -1 d 14 d 13 d 12 d 2 d 1 d 0 d 3 /wp /rp multiplexer cui wsm status / id register 128 word page buffer main block 32kw standby when /ce is at vih, the device is in the standby mode and its power consumption is reduced. data input/output are in a high-impedance(high-z) state. if the memory is deselected during block erase or program, the internal control circuits remain active and the device consume normal active power until the operation completes. ry/by ready/busy output a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 main block 32kw main block 16kw parameter block2 4kw parameter block1 4kw boot block 8kw address inputs /byte chip enable input output enable input write enable input write protect input reset/power down input byte enable input output disable when /oe is at vih, output from the devices is disabled. data input/output are in a high-impedance(high-z) state.
mitsubishi lsis m5m29fb/t800fp,vp,rv-80,-10,-12 may 1997 , rev.6.1 8,388,608-bit (1048,576-word by 8-bit / 524,288-word by16-bit) cmos 3.3v-only, block erase flash memory 3 software command definitions the device operations are selected by writing specific software command into the command user interface. read array command (ffh) the device is in read array mode on initial device powerup and after exit from deep powerdown, or by writing ffh to the command user interface. the device remains in read array mode until the other commands are written. read device identifier command (90h) though prom programmers can normally read device identifier codes by raising a 9 to v id , multiplexing high voltage onto address lines is not desired for micro-processor system. it is an other means to read device identifier codes that read device identifier code command(90h) is written to the command latch. following the command write, the manufacturer code and the device code can be read from address 0000h and 0001h, respectively. read status register command (70h) the status register is read after writing the read status register command of 70h to the command user interface. the contents of status register are latched on the later falling edge of /oe or /ce. so /ce or /oe must be toggled every status read. clear status register command (50h) the erase status and program status bits are set to "1"s by the write state machine and can only be reset by the clear status register command of 50h. these bits indicates various failure conditions. data protection the m5m29fb/t800 provides selectable block locking of memory blocks. each block has an associated nonvolatile lock-bit which determines the lock status of the block. in addition, the m5m29fb/t800 has a master write protect pin (wp) which prevents any modifications to memory blocks whose lock-bits are set to "0", when /wp is low. when /wp is high or /rp is v hh , all blocks can be programmed or erased regardless of the state of the lock-bits, and the lock-bits are cleared to "1" by erase. power supply voltage when the power supply voltage (vcc) is less than 2.2v, the device is set to the read-only mode. a delay time of 2 us is required before any device operation is initiated. the delay time is measured from the time vcc reaches vccmin (3.0v). during power up, /rp=gnd is recommended. falling in busy status is not recommended for possibility of damaging the device. block erase / confirm command (20h/d0h) automated block erase is initiated by writing the block erase command of 20h followed by the confirm command of d0h. an address within the block to be erased is required. the wsm executes iterative erase pulse application and erase verify operation. page program commands (41h) page program allows fast programming of 128words of data. writing of 41h initiates the page program operation. from 2nd cycle to 129th cycle write data must be serially inputted. address a6-0 have to be incremented from 00h to 7fh. after completion of data loading, the wsm controls the program pulse application and verify operation. basically re-program must not be done on a page which has already programmed. suspend/resume command (b0h/d0h) writing the suspend command of b0h during block erase operation interrupts the block erase operation and allows read out from another block of memory. writing the suspend command of b0h during program operation interrupts the program operation and allows read out from another block of memory. the device continues to output status register data when read, after the suspend command is written to it. polling the wsm status and suspend status bits will determine when the erase operation or program operation has been suspended. at this point, writing of the read array command to the cui enables reading data from blocks other than that which is suspended. when the resume command of d0h is written to the cui, the wsm will continue with the erase or program processes.
mitsubishi lsis m5m29fb/t800fp,vp,rv-80,-10,-12 may 1997 , rev.6.1 8,388,608-bit (1048,576-word by 8-bit / 524,288-word by16-bit) cmos 3.3v-only, block erase flash memory 4 1) x at ry/by is v ol or v oh(hi-z) . *the ry/by is an open drain output pin and indicates status of the internal wsm. when low,it indicates that the wsm is busy performing an operation. a pull-up resistor of 10k-100k ohms is required to allow the ry/by signal to transition high indicating a ready wsm condition. 2) x can be v ih or v il for control pins. bus operations 32kword main block 32kword main block 32kword main block 32kword main block 32kword main block 32kword main block 32kword main block 32kword main block 32kword main block 32kword main block 32kword main block 32kword main block 32kword main block 32kword main block 32kword main block 16kword main block 4kword parameter block 4kword parameter block 8kword boot block m5m29fb800 memory map 8kword boot block 32kword main block 32kword main block 32kword main block 32kword main block 32kword main block 32kword main block 32kword main block 32kword main block 32kword main block 32kword main block 32kword main block 32kword main block 32kword main block 32kword main block 16kword main block 4kword parameter block 4kword parameter block 32kword main block m5m29ft800 memory map 78000h-7ffffh 70000h-77fffh 68000h-6ffffh 60000h-67fffh 58000h-5ffffh 50000h-57fffh 48000h-4ffffh 40000h-47fffh 38000h-3ffffh 30000h-37fffh 28000h-2ffffh 20000h-27fffh 18000h-1ffffh 10000h-17fffh 08000h-0ffffh 04000h-07fffh 03000h-03fffh 02000h-02fffh 00000h-01fffh f0000h-fffffh e0000h-effffh d0000h-dffffh c0000h-cffffh b0000h-bffffh a0000h-affffh 90000h-9ffffh 80000h-8ffffh 70000h-7ffffh 60000h-6ffffh 50000h-5ffffh 40000h-4ffffh 30000h-3ffffh 20000h-2ffffh 10000h-1ffffh 08000h-0ffffh 06000h-07fffh 04000h-05fffh 00000h-03fffh a -1 -a 18 (bytemode) a 0 -a 18 (wordmode) 7e000h-7ffffh 7d000h-7dfffh 7c000h-7cfffh 78000h-7bfffh 70000h-77fffh 68000h-6ffffh 60000h-67fffh 58000h-5ffffh 50000h-57fffh 48000h-4ffffh 40000h-47fffh 38000h-3ffffh 30000h-37fffh 28000h-2ffffh 20000h-27fffh 18000h-1ffffh 10000h-17fffh 08000h-0ffffh 00000h-07fffh fc000h-fffffh fa000h-fbfffh f8000h-f9fffh f0000h-f7fffh e0000h-effffh d0000h-dffffh c0000h-cffffh b0000h-bffffh a0000h-affffh 90000h-9ffffh 80000h-8ffffh 70000h-7ffffh 60000h-6ffffh 50000h-5ffffh 40000h-4ffffh 30000h-3ffffh 20000h-2ffffh 10000h-1ffffh 00000h-0ffffh a -1 -a 18 (bytemode) a 0 -a 18 (wordmode) x8 ( bytemode) x16 ( wordmode) x8 ( bytemode) x16 ( wordmode) 1) mode array status register identifier code stand by program erase write read pins /ce /oe /we v il v il v il v il v ih v il v il v il v il v il v ih x v ih v ih v ih v ih v ih v ih x v il v il data out status register data identifier code hi-z hi-z command/data in command output disable deep power down others /rp v ih v ih v ih v ih v ih v ih v ih ry/by v oh (hi-z) x x x x x x v il v ih x v il x hi-z v ih v il x command bus operations for word-wide mode ( / byte =v ih ) dq 0-15 2) v ih lock bit status v il v il v ih lock bit data (dq 6 ) x v oh (hi-z) v oh (hi-z) 1) mode array status register identifier code stand by program erase write read pins /ce /oe /we dq 0-7 v il v il v il v il v ih v il v il v il v il v il v ih x v ih v ih v ih v ih v ih v ih x v il v il data out status register data identifier code hi-z hi-z command/data in command output disable deep power down others /rp v ih v ih v ih v ih v ih v ih v ih ry/by x x x x x x v il v ih x v il x hi-z v ih v il x command bus operations for byte-wide mode ( byte =v il ) 2) lock bit status v il v il v ih v ih lock bit data (dq 6 ) x v oh (hi-z) v oh (hi-z) v oh (hi-z)
mitsubishi lsis m5m29fb/t800fp,vp,rv-80,-10,-12 may 1997 , rev.6.1 8,388,608-bit (1048,576-word by 8-bit / 524,288-word by16-bit) cmos 3.3v-only, block erase flash memory 5 block locking d 6 provides lock status of each block after writing the read lock status command (71h). in case of tsop package, /wp pin must not be switched during performing read / write operations or wsm busy (wsms = 0). /rp /wp lock bit(internally) v il v hh v ih v ih v ih x x v il v il v ih x x x 0 1 write protection provided all blocks locked (deep power down mode) blocks locked (depend on lock bit data) all blocks unlocked blocks unlocked (depend on lock bit data) all blocks unlocked status register status erase status program status definition symbol (d 5 ) (d 4 ) write state machine status (d 7 ) (d 6 ) reserved (d 1 ) (d 0 ) (d 3 ) reserved (d 2 ) "1" "0" ready busy suspended operation in progress / completed error successful error successful - - - - sr.5 sr.4 sr.7 sr.6 sr.1 sr.0 sr.3 sr.2 block status after program device sleep status device in sleep suspend status device identifier code code manufacturer code pins hex. data 1ch d 0 0 a 0 v il d 1 0 d 2 1 d 3 1 d 4 1 d 5 0 d 6 0 d 7 0 device code (-t) 5dh 0 v ih 1 1 1 1 0 1 0 device code (-b) 5eh 0 v ih 1 1 1 1 0 1 0 in the word-wide mode, the same data as d 7-0 is read out from d 15-8 . a 9 = v hh mode : a 9 = 11.5v~13.0v set a9 to v hh min.200ns before falling edge of /ce in ready status. min.200ns after return to v ih , device can't be accessed. a 1 ~a 8 , a 10 ~a 18, /ce,/oe = vil, /we = v ih d 15 /a -1 = v il (/byte = l) *the ry/by is an open drain output pin and indicates status of the internal wsm. when low,it indicates that the wsm is busy performing an operation. a pull-up resistor of 10k-100k ohms is required to allow the ry/by signal to transition high indicating a ready wsm condition. error successful device not in sleep *d3 indicates the block status after the page programming. when d3 is "1", the page has the over-programed cell . if over-program occures, the device is block fail. however if d3 is "1", please try the block erase to the block. the block may revive. software command definition command list read array ffh x write 3rd bus cycle 1st bus cycle 2nd bus cycle command address mode data address mode data address mode data device identifier 90h x write id ia read read status register 70h x write srd x read clear status register 50h x write page program x write wd0 write 41h x write wa0 write wd1 wa1 write block erase / confirm 20h x write d0h ba write suspend b0h x write resume 71h x write 2) 3) 5) 6) 4) read lock bit status lock bit program / confirm erase all unlocked blocks write write x x a7h 77h d0h write read ba ba x d0h d0h dq6 2) (d 7-0 ) (d 7-0 ) (d 7-0 ) 1) in the word-wide mode, upper byte data (d8-d15) is ignored. 2) ia=id code address : a0=vil (manufacturer's code) : a0=vih (device code), id=id code, /byte =vil : a-1, a1-a18 = vil, /byte =vih : a1-a18 = vil 3) srd = status register data 4) wa=write address, wd=write data. /byte =vil : write address and write data must be provided sequentially from 00h to ffh for a-1-a6. page size is 256byte (256byte x 8bit), /byte =vih : write address and write data must be provided sequentially from 00h to 7fh for a0-a6. page size is 128word (128word x 16bit). 5) ba = block address ( addresses except block address mest be vih.) 6) dq6 provides block lock status, dq6 = 1 : block unlock, dq6 = 0 : block locked. 7) sleep command (f0h) put the device into the sleep mode after completing the current operation. the active current is reduced to deep power -down levels. the read array command (ffh) must be written to get the device out of sleep mode. 4) 4) sleep write x f0h 7) /rp v il v hh v ih v ih lock bit(internally) x x 0 1 sop package tsop package
mitsubishi lsis m5m29fb/t800fp,vp,rv-80,-10,-12 may 1997 , rev.6.1 8,388,608-bit (1048,576-word by 8-bit / 524,288-word by16-bit) cmos 3.3v-only, block erase flash memory 6 capacitance symbol parameter test conditions pf pf unit max 8 12 typ min limits ta = 25?, f = 1mhz, v in = v out = 0v input capacitance (address, control pins) output capacitance c in c out conditions absolute maximum ratings parameter with respect to ground symbol v cc all input or output voltage except v cc, a9,/rp v i1 v cc voltage 1) unit v v min max 4.6 -0.2 -0.6 14.0 ambient temperature temperature under bias t a t bs storage temperature t stg ? ? ? 0 70 -10 80 -65 125 output short circuit current i out ma 100 v i2 a9,rp supply voltage -0.6 4.6 v 1) minimum dc voltage is -0.5v on input/output pins. during transitions, this level may undershoot to -2.0v for periods <20ns. maximum dc voltage on input/output pins is v cc +0.5v which, during transitions, may overshoot to v cc +1.5v for periods <20ns. dc electrical characteristics (ta = 0 ~ 70?, vcc = 3.3v?.3v, unless otherwise noted) symbol parameter max typ1) limits min test conditions unit v cc standby current i lo ?0 output leakage current ? 0v v out v cc i li input leakage current ? 0v v in v cc ?.0 v cc deep powerdown current output high voltage v v ol output low voltage v i ol = 5.8ma 0.45 vcc+0.5 v ih input high voltage v 2.0 0.8 v il input low voltage ?0.5 v oh1 i oh = ?.5ma 0.85vcc v v oh2 i oh = ?00? vcc?.4 v all currents are in rms unless otherwise noted. 1) typical values at vcc=3.3v, ta=25? 2) to protect against initiation of write cycle during vcc power-up/ down, a write cycle is locked out for vcc less than v lko. if vcc is less than v lko, write state machine is reset to read mode. when the write state machine is in busy state, if vcc is less than v lko , the alteration of memory contents may occur. i cc3 v cc program current ma 40 v cc = 3.6v, v in =v il /v ih , /ce = /rp =/wp = v ih i cc4 v cc erase current ma 40 v cc = 3.6v, v in =v il /v ih , /ce = /rp =/wp = v ih v id a9 intelligent identifier voltage 11.4 12.6 v 12.0 v ihh 11.4 12.6 v /rp unlock voltage 12.0 v lko low v cc lock-out voltage 2) 1.5 2.5 v i rp /rp all block unlock current /rp = v hh max 100 ? i id a9 intelligent identifier current a9 = v id max 100 ? i cc5 v cc suspend current 200 v cc = 3.6v, v in =v il /v ih , /ce = /rp =/wp = v ih ? i sb2 5 v cc = 3.6v, v in =gnd or v cc , /ce = /rp = /wp= v cc ?.3v ? 1 25 ma i cc1 v cc read current for word or byte v cc = 3.6v, v in =v il /v ih , /ce = v il , /rp=oe=v ih , f = 10mhz, i out = 0ma 7 i sb1 v cc = 3.6v, v in =v il /v ih , /ce = /rp =/wp = v ih ? 200 50 i cc2 30 ma v cc write current for word or byte v cc = 3.6v,v in =v il /v ih , /ce =/we= v il , /rp=/oe=v ih v cc = 3.6v, v in =v il /v ih , /rp = v il ? 15 5 i sb3 ? 1 i sb4 v cc = 3.6v, v in =gnd or v cc , /rp =gnd?.3v 5
mitsubishi lsis m5m29fb/t800fp,vp,rv-80,-10,-12 may 1997 , rev.6.1 8,388,608-bit (1048,576-word by 8-bit / 524,288-word by16-bit) cmos 3.3v-only, block erase flash memory 7 read-only mode ac electrical characteristics (ta = 0 ~70?, vcc = 3.3?.3v) write mode (/we control) ac electrical characteristics (ta = 0 ~ 70?, vcc = 3.3v?.3v) symbol parameter unit max min max min limits m5m29fb/t800-10 m5m29fb/t800-12 timing measurements are made under ac waveforms for read operations. typ typ read timing parameters during command write operations mode are the same as during read-only operations mode. typical values at vcc=3.3v, ta=25? max min m5m29fb/t800-80 t a (ad) address access time ns 100 120 t avqv 80 t clz chip enable to output in low-z ns 0 0 t elqx 0 t a (ce) chip enable access time ns 100 120 t elqv 80 t a (oe) output enable access time ns 50 60 t glqv 40 t df(ce) chip enable high to output in high z ns 25 30 t ehqz 25 t rc read cycle time ns 100 120 t avav 80 /byte low to output high-z ns 30 25 t bhz t flqz 25 typ t whgl /oe hold from /we high t oeh /ce low to /byte high or low t bcd ns 5 5 t elfl/h 5 ns 100 120 80 ns 0 0 0 t oh output hold from /ce, /oe, addresses t oh /byte access time ns 120 100 t a(byte) 80 t fl/hqv t olz ns 0 0 t glqx 0 output enable to output in low-z t df(oe) ns t ghqz output enable high to output in high z 25 30 25 t phz /rp low to output high-z ns t plqz 150 300 150 t bad ns address to /byte high or low t avfl/h 5 5 5 /rp recovery to /ce low ns t ps t phel 500 500 500 symbol parameter unit max min max min limits m5m29fb/t800-10 m5m29fb/t800-12 typ typ max min m5m29fb/t800-80 t wc t avav write cycle time ns 100 120 80 t dh t whdx data hold time ns t ds t dvwh data set-up time ns 50 50 50 t ah t whax address hold time ns 10 t as t avwh address set-up time ns 50 50 50 t wp t wlwh write pulse width ns 60 60 60 t ch t wheh chip enable hold time ns t cs t elwl chip enable set-up time ns 0 0 0 t wph t whwl write pulse width high ns 20 20 20 t ps t phwl /rp high recovery to write enable low ns 500 500 500 t bls t blh block lockhold from valid srd ns 0 0 t qvph 0 t whrl t whrl write enable high to ry/by low ns 100 120 80 t dap t whrh1 duration of auto-program operation ms 7.5 120 120 7.5 7.5 120 t dae t whrh2 duration of auto-block erase operation 50 600 50 600 ms 50 600 typ block lock set-up to write enable high ns 100 120 t phhwh 80 t wph t bs t fl/hwh byte enable high or low set-up time ns 50 50 50 t bh t whfl/h byte enable high or low hold time ns 100 120 80 t wps 10 10 10 10 10 0 0 0
mitsubishi lsis m5m29fb/t800fp,vp,rv-80,-10,-12 may 1997 , rev.6.1 8,388,608-bit (1048,576-word by 8-bit / 524,288-word by16-bit) cmos 3.3v-only, block erase flash memory 8 write mode (/ce control) ac electrical characteristics (ta = 0 ~ 70?, vcc = 3.3v?.3v) read timing parameters during command write operations mode are the same as during read-only operations mode. typical values at vcc=3.3v, ta=25? erase and program performance block erase time main block write time (page mode) page write time parameter ms sec ms unit typ 7.5 1.9 50 max 120 3.8 600 min vcc power up / down timing symbol unit typ 2 max min t vcs parameter /rp =v ih set-up time from vccmin ? during power up/down, by the noise pulses on control pins, the device has possibility of accidental erasure or programming. the device must be protected against initiation of write cycle for memory contens during power up/down. the delay time of min.2?ec is always required before read operation or write operation is initiated from the time vcc reaches vccmin during power up/down. by holding /rp v il , the contens of memory is protected during vcc power up/down. during power up, /rp must be held v il for min.2? from the time vcc reaches vccmin. during power down, /rp must be held v il until vcc reaches gnd. /rp doesn't have latch mode ,so / rp must be held v ih during read operation or erase/program operation. symbol parameter unit max min max min limits m5m29fb/t800-10 m5m29fb/t800-12 typ typ max min m5m29fb/t800-80 t wc t avav write cycle time ns 100 120 80 t dh t ehdx data hold time ns t ds t dveh data set-up time ns 50 50 50 t ah t ehax address hold time ns t as t aveh address set-up time ns 50 50 50 t cep t eleh /ce pulse width ns 60 60 60 t wh t ehwh write enable hold time ns 0 0 0 t ws t wlel write enable set-up time ns 0 0 0 t ceph t ehel /ce pulse width high ns 20 20 20 t ps t phel /rp high recovery to write enable low ns 500 500 500 t bls t blh block lockhold from valid srd ns 0 0 t qvph 0 t ehrl t ehrl /ce enable high to ry/by low ns 100 120 80 t dap t ehrh1 duration of auto-program operation ms 7.5 120 120 7.5 7.5 120 t dae t ehrh2 duration of auto-block erase operation 50 600 50 600 ms 50 600 typ block lock set-up to write enable high ns 100 120 t phheh 80 t wph t bs t fl/heh byte enable high or low set-up time ns 50 50 50 t bh t ehfl/h byte enable high or low hold time ns 100 120 80 t wps 10 10 10 10 10 10
mitsubishi lsis m5m29fb/t800fp,vp,rv-80,-10,-12 may 1997 , rev.6.1 8,388,608-bit (1048,576-word by 8-bit / 524,288-word by16-bit) cmos 3.3v-only, block erase flash memory 9 test conditions for ac characteristics input voltage : v il = 0v, v ih = 3.0v input rise and fall times : 5ns (80ns) 10ns (100/120ns) reference voltage at timing measurement : 1.5v output load : 1ttl gate + cl(100pf for 100/120ns) cl(30pf for 80ns) or ac waveforms for read operation and test conditions output valid high-z t df(oe) t rc v ih v il v ih v il v ih v il v ih v il v oh v ol addresses /ce /oe /we data address valid 3.3v gnd v cc t oh t olz t a (ce) t oeh t clz t a (ad) t a (oe) high-z dut 3.3k w 1n914 1.3v c l =30/100pf v ih v il /rp t ps v ih v il v ih v il v ih v il v ih v il addresses (a 0 - a 18 ) address valid /ce /byte data (d 0 - d 7 ) byte ac waveforms for read operation t a(ad) high-z v ih v il data (d 8 - d 14 ) high-z v ih v il d 15 / a -1 t a(byte) t bhz valid valid output valid valid a -1 d 15 a -1 v ih v il /oe when /byte=v ih , /ce=/oe=v il , d 15 /a -1 is output status. at this time, input signal must not be applied. address valid t a(ad) t a(ce) t a(oe) t a(byte) t bcd t bad t clz t olz t bad t oh t df(oe) t df(ce) t df(ce) t phz vcc power up / down timing v ih v il /rp read /write inhibit t vcs v ih v il /ce v ih v il /we t ps t ps read /write inhibit read /write inhibit
mitsubishi lsis m5m29fb/t800fp,vp,rv-80,-10,-12 may 1997 , rev.6.1 8,388,608-bit (1048,576-word by 8-bit / 524,288-word by16-bit) cmos 3.3v-only, block erase flash memory 10 ac waveforms for erase operations (/we control ) 41h din t wph t wp t ds t dh t cs t ch t wc v ih v il v ih v il v ih v il v ih v il a 7 ~a 18 address valid /ce /oe /we data ry/by t ah v ih /byte v oh v ol v il /byte = v il ( a -1 ~ a 6 ) 00h 01h ffh 02h~feh t as din din srd din v ih v il t oeh t dae, t dap t whrl program read status register write read array command ac waveforms for page program operation (/we control ) ffh t ps v ih v il /rp v ih v il /wp t wph t wps v hh 20h d0h t wph t wp t ds t dh t cs t ch t wc v ih v il v ih v il v ih v il v ih v il ry/by t ah v ih v oh v ol v il addresses t as ffh srd t oeh t dap ,t dae t whrl address valid erase read status register write read array command v il v ih v il t ps v ih /byte /ce /oe /we data /rp /wp t bls t blh v hh /byte = v ih ( a 0 ~ a 6 ) 7fh 02h~7eh 01h 00h t a(ce) t a(oe) t blh t bls v ih v il t bs t bh t a(oe) t a(ce) t wps t wph v ih v il t bs t bh
mitsubishi lsis m5m29fb/t800fp,vp,rv-80,-10,-12 may 1997 , rev.6.1 8,388,608-bit (1048,576-word by 8-bit / 524,288-word by16-bit) cmos 3.3v-only, block erase flash memory ac waveforms for erase operations (/ce control ) ac waveforms for page program operation (/ce control ) 11 41h din t ceph t cep t ds t dh t ws t wh t wc v ih v il v ih v il v ih v il v ih v il a 7 ~a 18 address valid /ce /oe /we data ry/by t ah v ih /byte v oh v ol v il /byte = v il ( a -1 ~ a 6 ) 00h 01h ffh 02h~feh t as din din srd din v ih v il t oeh t dae, t dap t ehrl program read status register write read array command ffh t ps v ih v il /rp v ih v il /wp t wph t wps v hh /byte = v ih ( a 0 ~ a 6 ) 7fh 02h~7eh 01h 00h t a(ce) t a(oe) t blh t bls v ih v il t bs t bh 20h d0h t ceph t cep t ds t dh t ws t wh t wc v ih v il v ih v il v ih v il v ih v il ry/by t ah v ih v oh v ol v il addresses t as ffh srd t oeh t dap ,t dae t ehrl address valid erase read status register write read array command v il v ih v il t ps v ih /byte /ce /oe /we data /rp /wp t bls t blh v hh t a(oe) t a(ce) t wps t wph v ih v il t bs t bh
mitsubishi lsis m5m29fb/t800fp,vp,rv-80,-10,-12 may 1997 , rev.6.1 8,388,608-bit (1048,576-word by 8-bit / 524,288-word by16-bit) cmos 3.3v-only, block erase flash memory 12 full status check procedure sr.5 = 0 ? sr.4 = 0 ? sr.4 =1 and sr.5 =1 ? successful (block erase, program) yes yes yes no status register read command sequence error no block erase error no program error (block) write 77h write d0h block address lock bit program flow chart sr.4 = 0 ? lock bit program successful yes yes no no start lock bit program failed sr.7 = 1 ? sr.3 = 0 ? yes no program error (page, lock bit) page program flow chart start write 41h full status check if desired page program completed yes n = 0 n = n+1 write address n, data n yes sr.7 = 1 ? n = ffh ? or n = 7fh ? no write b0h ? yes no suspend loop write d0h yes no status register read
mitsubishi lsis m5m29fb/t800fp,vp,rv-80,-10,-12 may 1997 , rev.6.1 8,388,608-bit (1048,576-word by 8-bit / 524,288-word by16-bit) cmos 3.3v-only, block erase flash memory 13 suspend / resume flow chart start write b0h operation resumed sr.6 =1? yes no write ffh read array data done reading ? no yes write d0h suspend resume block erase flow chart start write 20h write d0h block address full status check if desired yes sr.7 = 1 ? write b0h ? yes no suspend loop write d0h yes no status register read block erase completed status register read sr.7 = 1? yes no program / erase completed
mitsubishi lsis m5m29fb/t800fp,vp,rv-80,-10,-12 may 1997 , rev.6.1 8,388,608-bit (1048,576-word by 8-bit / 524,288-word by16-bit) cmos 3.3v-only, block erase flash memory 14 operation status and effective command page program setup lock bit program setup block erase setup f0h setup state internal state sleep state read/standby state [sleep] other erase & verify read status register request sleep f0h return b0h d0h b0h d0h ready is request sleep? y n 50h 41h 77h 20h a7h suspend state read array read status register read device identifier read lock status ffh 70h 90h 70h 90h ffh ffh 71h 70h 90h 71h 90h invalid data read status register read device identifier read lock status ffh 70h 90h 70h 90h ffh ffh 71h 70h 71h 90h read array read status register 70h 90h ffh [wake up / read array] other other d0h d0h d0h wdi i=0-255 read device identifier erase all unlocked blocks setup program & verify read status register request sleep f0h return 71h 71h 50h ffh ffh ffh clear status register read lock status 71h 71h 70h 90h

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